1. Field of the Invention
The present invention relates to a structure and manufacturing method of a power metal oxide silicon field effect transistor (hereinafter referred to as "MOSFET"), and particularly to a structure and manufacturing method of a high voltage MOSFET which obtains, a high breakdown voltage with an area small enough to fit for the use of smart power IC, and provided with a metal field plate to reduce any specific-on-resistance.
2. Description of the Prior Art
Since the power MOSFET has an excellent switching speed compared with other power elements, and a characteristic that it has low on-resistance at any element of relative low resisting pressure less than 300(V), the high voltage lateral power MOSFET gets into the spotlight as power element for the very large-scale integrated circuit.
As power elements in general use, there are double-diffused MOSFET (DMOSFET), insulated gate bipolar transistor (IGBT), bipolar transistor, etc., but as complementary metal oxide semiconductor (CMOS) VLSI for low voltage, and elements for high voltage (10V to 500V), the lateral double-diffused MOSFET (hereinafter referred to as "LDMOSFET") is developed as most effective element.
In FIG. 1(A) there is shown a sectional structure of a general LDMOSFET used widely for smart power IC. The manufacturing process of the said LDMOSFET is described briefly as follows:
In the first place, a drift area (11) to prevent any high voltage is made on a silicon substrate (13) by the epitaxial layer growth method or well forming process using diffusion, and a field oxide (4) is formed on the surface of substrate between the channel (8) and the drain (10) using the process of the local oxidation of silicon.
In the next step, an oxide film is grown as gate-insulating film on the entire surface of the substrate including the said field oxide(4), and then n+ polycrystalline silicon film is formed by implementing POCl3 diffusion after depositing the polycrystalline silicon film on the said oxide film.
In the next step, a polycrystalline silicon gate (1) is formed by selecting and etching the said N+ polycrystalline silicon film using a photosensitive mask, and after self-align to the polycrystalline silicon gate on the side of source, and ion-injection of p-dopants, the drive-in is performed. As a result, a double-diffused well (or p-well) is formed.
In the continuous step, a source(6) and a drain(10) are formed by an ion-injection of n-dopants in the specified parts of the right and left sides of the said polycrystalline silicon gate(1), and p+ area, a body contact (5) is formed at a location adjacent to the said source(6), by implementing the ion-injection of p-dopants after forming a photosensitive mask on the said source(6).
Subsequently, an oxide film and an insulation film are deposited to the substrate including the said polycrystalline silicon gate(1), and the surface of such oxide film is evened by reflowing it at the temperature of 900 C. to 1000 C., and the ion-injected dopants are activated simultaneously.
Then, a contact hole is formed by etching the oxide film with a mask for forming the contact, to the extent that the specified part of the said source(6) and the specified parts of the body contact(5) and drain are exposed, and after depositing a metal film over the entire surface of oxide film including the said contact hole, a metal lead, for example, a source electrode(2) and a drain electrode(3) are formed by selecting and etching it, respectively.
Finally, the manufacture of elements are completed by depositing an insulation film, for example an oxide film as a passivation layer to protect the element, over the entire surface of the oxide film including the said source and drain electrodes 2, 3), and opening then the pad.
Accordingly, in case of n-channel high voltage LDMOSFET, an inversion layer is formed in the channel area(8) when a voltage higher than the threshold voltage is applied, and if a voltage higher than that of the source electrode(2) terminal is applied at that time to the drain electrode(3) terminal, the electrons are supplied from source(6) to channel(8), through the surface drift area(9) in the lower part of the field oxide(4), to the drain(10), and which makes the current flow.
Although the said elements may be employed in diversified ways in high side driver (HSD), low side driver (LSD) and H-bridge circuits within chips, and it is easily manufactured, there are disadvantages that the subthreshold slope is so large due to ununiformity of the doping concentration in the channel area which is the structure of LDMOSFET itself, that the threshold voltage is risen, and that a breakdown phenomenon occurs on the silicon substrate surface in drift area near the channel.
In FIG. 1(B) is shown a structure of a reduced surface field (RESURF) LDMOSFET in which the performance of LDMOSFET as described in FIG. 1(A) is improved.
In comparison with drift area made by the LDMOSFET as described in FIG. 1(A) on substrate using the epitaxial growth method or well formation process, so as to include all the parts in which source, drain and field oxide(4) are formed, in the said element, the drift area is formed so as to have the minimum area, by implementing ion-injection and drive-in or epitaxial layer formation in parts in which field oxide(4) and drain(10) are formed, in a manner that such parts are adjacent to the said D-well(7), as shown in FIG. 1(B) to use the RESURF principles.
To form the elements by the said way is to improve the breakdown phenomenon and conduction resistance on the silicon substrate surface which are disadvantages of the LDMOSFET as shown in FIG. 1(A), and has advantages that it may obtain high breakdown voltage and low conduction resistance with the minimum area, by forming the drift layer as well-type or epitaxial layer.
However, such an element has disadvantages in that it may be used only as LSD, for p-type substrate(12) is connected to the source and the body contact(5), and it being of the DMOS structure, it is inevitable to have a high threshold voltage due to ununiformal doping concentration of the channel.
In FIG. 1(C) is shown the RESURF extended drain MOSFET (EDMOSFET) for improving the threshold voltage characteristics of such LDMOSFET and eliminating the restriction on the scope of application which is a shortcoming of the RESURF LDMOSFET.
The said element has no D-well (or p-well) as shown in FIGS. 1(A) and 1(B).
Since the doping concentration in the channel area is uniform, the threshold voltage may be r educed, and for the purpose of obtaining any desires threshold voltage, it is possible to adjust the threshold voltage to a desired one by carrying out a threshold voltage adjustment ion-injection into the channel area(8), as in the low voltage MOSFET.
In case of n-channel high voltage RESURF EDMOSFET, therefore, the most high voltage applied to the drain electrode(3) terminal is applied to the drift area(11), and some voltage is applied to the channel area(8). In this case, when a voltage higher than the threshold voltage is applied to a polycristalline silicon gate(1), an inversion layer is formed in the channel area(8), and when a voltage lower than that of the drain electrode(3) terminal is applied to the source electrode(2) terminal, electrons flow from the source(6) through the channel area(8) and drift area(11) to the drain(10).
As reported by O. K. Kwon et al., "Optimized 60 V Lateral DMOS Device for VLSI Power Applications," 1991 Symposium on VLSI Technology, Oiso, Japan, pp.115-116, however, the above-mentioned element has also disadvantages in that since the electrons having passed through the channel area(8) flow below the field oxide transiting the surface drift area(9), and the current conduction path is distorted, a high conduction resistance is inevitable.